library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity AOUT is
	Port ( a : in STD_LOGIC_VECTOR (15 downto 0);
		astr : in STD_LOGIC;
		clkin : in STD_LOGIC;
		z : out STD_LOGIC_VECTOR (15 downto 0);
		zstr : out STD_LOGIC;
		aack : out STD_LOGIC);
end AOUT;

architecture Behavioral of AOUT is
	begin
	dados: process(clkin, astr)
	begin
		if clkin'event and clkin = '1' then
			z <= "ZZZZZZZZZZZZZZZZ";
			zstr <= '0';
			aack <= '0';
			if astr = '1' then
				z <= a;
				zstr <= '1';
				aack <= '1';
			end if;
		end if;
	end process dados;
end Behavioral;